Conventionally, information to be transmitted (such as image data, audio data, etc.) is converted into a digital signal, and the digital signal is then modulated into a high-frequency carrier wave (carrier frequency) to obtain a high-frequency digitally modulated signal which is transmitted to a receiving device via a space or a transmission path.
In this case, frequency bands of the modulated carrier wave are determined at a predetermined interval on the basis of each information piece to be transmitted, and a plurality of information pieces are respectively allotted to the plurality of frequency bands.
On the receiving device side, the frequency bands are continuously received, and only a particular high-frequency digitally modulated signal is extracted by a tuner section (analog section). The extracted particular high frequency digitally modulated signal is converted into a digital signal by an AD converter. The digital signal is then demodulated into a digital signal corresponding to the digital signals yet to be modulated, through a digital signal processing performed by a demodulating section (digital section).
An input level of the signal handled by the tuner section is not constant. This is because the tuner section extracts the particular high-frequency signal amongst digitally modulated high-frequency signals of the frequency bands. Accordingly, it is required that the tuner section be capable of appropriately receiving even if the input level is remarkably low. This necessitates reduction of influence of noise radiated from inside or outside the receiving device. Furthermore, downsizing of the receiving device is also required for the purpose of use in a mobile communications terminal such as a mobile phone.
Patent document 1 (Japanese Unexamined Patent Publication No. 14015/1993 (Tokukaihei 5-14015; published on Jan. 22, 1993)) discloses a high-frequency SMD module having a shielded high-frequency circuit, in which module: (i) a shield layer made of a GND pattern is set inside a multilayered substrate; (ii) a high-frequency circuit is mounted on a side, of the GND pattern, which is closer to the surface of the multilayered substrate; and (iii) the high-frequency circuit is provided thereon with a shield cap, and is connected to the GND pattern. Further, a resistor constituting the high-frequency circuit is set in the form of printed resistor, on the bottom-face side of the multilayered substrate, for the purpose of downsizing the receiving device.
Further, Patent document 2 (Japanese Unexamined Patent Publication No. 197662/1998 (Tokukaihei 10-197662; published on Jul. 31, 1998)) discloses a receiving device, aimed at downsizing by: (i) arranging, on one surface of a circuit wiring board, a receiving antenna section and a receiving circuit digital circuit section; (ii) arranging, on another surface of the circuit wiring board, a receiving circuit analog circuit section: and (iii) interposing an electromagnetic shield layer in the circuit wiring board.
Furthermore, in the field of printed circuit board, Patent document 3 (Japanese Unexamined Patent Publication No. 353895/2000 (Tokukai 2000-353895; published on Dec. 19, 2000)) discloses a printed circuit board including: a digital circuit-use GND layer arranged on the entire surface of an internal layer of a substrate; and an analog circuit-use GND layer which is arranged in an internal layer of an analog signal processing section, and which is adjacent to the digital circuit use GND layer.
Here, the technology of Patent document 1 enables downsizing of the apparatus in the width direction by an amount of setting the resistor constituting the high-frequency circuit, on the bottom surface side of the multilayered substrate. However, there is a limit to an amount that can be reduced by this method.
Further, in the downsizing method of Patent document 2, the receiving circuit analog circuit section and the receiving circuit digital circuit section are not sufficiently isolated from each other. Therefore, harmonic signals generated by ON/OFF of signals output from the receiving circuit digital circuit section influences the receiving circuit analog circuit section.
More specifically, the amplitude of the output signal of the receiving circuit digital circuit section is considerably large for a voltage of the signal input to the receiving circuit analog circuit section. On this account, the harmonic signals are generated with the ON/OFF of the output signal. Although the circuit wiring board of Patent document 2 has therein the electromagnetic shield layer, a voltage of harmonic signal component (harmonic signal voltage) is generated when a harmonic signal current flows in a parasitic inductance occurring in the electromagnetic shield layer. As such, the electric potential of the electromagnetic shield layer is not 0V, but a value to which the harmonic signal voltage is added. This variation in the electric potential of the electromagnetic shield layer influences the tuner section.
One approach to solve this problem is to combine the technologies of Patent documents 2 and 3: i.e. to make the electromagnetic shield layer of Patent document 2 a multilayered structure having an analog GND and a digital GND, as is disclosed in Patent document 3.
This however causes the following problem. Namely, the analog GND and the digital GND are bonded due to a parasitic capacitance between the both GNDs, and the electric potential of the analog GND varies thereby influencing the receiving circuit analog circuit section.
This point is described in further detail. The parasitic capacitance between the both GNDs varies depending on the materials of the substrate, and the thickness of the insulation layer. However, it is sufficiently possible that a capacitance of approximately 100 pF is generated in some cases. In a case where the frequency handled by the receiving device is several hundred MHz, the impedance for a capacitance of 100 pF is of the order of several Ω. This is almost the same as connecting the analog GND and the digital GND in the substrate at several Ω.
As such, the harmonic signal current of the harmonic signal flowing in a buffer, which outputs output signals of the receiving circuit digital circuit section, partially flows into the analog GND side via the digital GND and the parasitic capacitance.
Further, each of the analog GND and the digital GND is lead to a terminal electrode for providing connection with a GND outside the receiving device. A parasitic capacitance is also generated there.
A voltage of harmonic signal component (harmonic signal voltage) is generated when a harmonic signal current flows in a parasitic inductance of the analog GND. As such, the electric potential of the analog GND is not 0V, but is a value to which the harmonic signal voltage is added. This variation in the electric potential of the GND influences the receiving circuit analog circuit section.
As described, an arrangement of a tuner section (analog section) and a demodulating section (digital section) in a close distance to each other, for the purpose of downsizing the receiving device, causes a problem that the tuner section which handles minute signal input is largely influenced by the harmonic signal generated by the demodulating section which handles signals of a large amplitude. Accordingly, in order to receive minute signals, the parasitic capacitance between the analog GND and the digital GND needs to be increased as much as possible.